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A Parallel Algorithm Synthesis Procedure For High-Performance Computer Arch...

Description: Please refer to the section BELOW (and NOT ABOVE) this line for the product details - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Title:A Parallel Algorithm Synthesis Procedure For High-Performance Computer ArchitecturesISBN13:9780306477430ISBN10:0306477432Author:Dunn, Ian N. (Author), Meyer, Gerard G. L. (Author)Description:Despite Five Decades Of Research, Parallel Computing Remains An Exotic, Frontier Technology On The Fringes Of Mainstream Computing Its Much-Heralded Triumph Over Sequential Computing Has Yet To Materialize This Is In Spite Of The Fact That The Processing Needs Of Many Signal Processing Applications Continue To Eclipse The Capabilities Of Sequential Computing The Culprit Is Largely The Software Development Environment Fundamental Shortcomings In The Development Environment Of Many Parallel Computer Architectures Thwart The Adoption Of Parallel Computing Foremost, Parallel Computing Has No Unifying Model To Accurately Predict The Execution Time Of Algorithms On Parallel Architectures Cost And Scarce Programming Resources Prohibit Deploying Multiple Algorithms And Partitioning Strategies In An Attempt To Find The Fastest Solution As A Consequence, Algorithm Design Is Largely An Intuitive Art Form Dominated By Practitioners Who Specialize In A Particular Computer Architecture This, Coupled With The Fact That Parallel Computer Architectures Rarely Last More Than A Couple Of Years, Makes For A Complex And Challenging Design Environment To Navigate This Environment, Algorithm Designers Need A Road Map, A Detailed Procedure They Can Use To Efficiently Develop High Performance, Portable Parallel Algorithms The Focus Of This Book Is To Draw Such A Road Map The Parallel Algorithm Synthesis Procedure Can Be Used To Design Reusable Building Blocks Of Adaptable, Scalable Software Modules From Which High Performance Signal Processing Applications Can Be Constructed The Hallmark Of The Procedure Is A Semi-Systematic Process For Introducing Parameters To Control The Partitioning And Scheduling Of Computation And Communication This Facilitates The Tailoring Of Software Modules To Exploit Different Configurations Of Multiple Processors, Multiple Floating-Point Units, And Hierarchical Memories To Showcase The Efficacy Of This Procedure, The Book Presents Three Case Studies Requiring Various Degrees Of Optimization For Parallel Execution This Book Can Be Used As A Reference For Algorithm Designers Or As A Text For An Advanced Course On Parallel Programming Binding:Hardcover, HardcoverPublisher:SpringerPublication Date:2003-04-30Weight:0.72 lbsDimensions:0.51'' H x 6.22'' L x 7.54'' WNumber of Pages:108Language:English

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Location: USA

End Time: 2024-09-23T14:50:24.000Z

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Book Title: A Parallel Algorithm Synthesis Procedure For High-Performanc...

Item Length: 9.3in

Item Width: 6.1in

Author: Ian N. Dunn, Gerard G. L. Meyer

Publication Name: Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures

Format: Hardcover

Language: English

Publisher: Springer

Publication Year: 2003

Series: Series in Computer Science Ser.

Type: Textbook

Item Weight: 28.2 Oz

Number of Pages: Xi, 108 Pages

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